As the semiconductor industry looks toward the 22 nm technology node and beyond, some manufacturers are considering a transition from planar CMOS transistors to the three-dimensional (3D) FinFET device architectures. In contrast to the gate in a planar transistor, which sits above the channel, the gate of a FinFET wraps around the channel, providing electrostatic control from multiple sides. Relative to planar transistors, such FinFETs offer improved channel control and, therefore, reduced short channel effects. Thanks to its intrinsically superior electrostatics control, the device electrostatics of FinFETs are improved as the width of the devices (Fin) is aggressively scaled (typically around 10-15 nm for sub-22 nm nodes applications). This is a result of the so-called “double gate” field effect, and can be quantified by significant DIBL reduction at small gate lengths (Lg), as the fin width (Wfin) reduces.
For the specific integration of FinFET on Bulk Silicon (Bulk-FinFET), the use of a “ground plane” right underneath the Si Fin has been studied. This ground plane is provided to prevent a potential leakage path between source and drain, in any regions which are low doped and not under direct control of the gate. In conventional Bulk-FinFETs, the ground plane is formed via implantation of a doped layer at an energy sufficiently high to cause the dopants to tunnel through the vertical length of the substrate and form the ground plane in the area of the well. The ground plane formation step is done after isolation features are formed. However, due to multiple factors (e.g., finite gradient of dopant profiles as-implanted, WPE, and backscattering from implantation into the isolation oxide layers), the Si fin can be unintentionally doped. The unintentional doping can degrade electrical performance, manifesting in matching issues (due to Random Dopant Fluctuation) or drive current variations (due to mobility loss from impurity scattering).
Moreover, in the case where this ground plane implant is performed after fin formation, any variation in the actual fin height will translate into a change of dopants position with respect to the top of the Fin. Therefore, the effective (or electrical) fin height of the device varies as well. Worst yet, the ground plane may not be properly formed. The variations in fin height are not only due to variations in process conditions, but also due to loading effects and other pattern dependencies. These variations will impact directly the key figures of merit of the devices (gate capacitance and drive current), directly proportional to the device effective width. As a result of such limitations, manufacturers are also considering utilizing SOI-FinFET device architectures, which eliminate the need for the heavily doped ground plane by simply providing Si fins on top of an insulator.
However, SOI-FinFET devices are not without issues. For example, one significant issue is the inability to provide an adequate backside substrate contact to fix a body voltage for the devices. This can lead to odd device characteristics, such as abrupt increases in current or a history effect which can alter threshold voltages (Vt) over time. Another significant issue is that the cost of an SOI substrate is prohibitive compared to bulk silicon.